Group Publications

All publications are listed in reverse chronological order within groups.

Hydra-specific Publications:

Parallel Programming Using Thread-level Speculation
Manohar Prabhu
Advisor: Kunle Olukotun
Doctoral Dissertation, Stanford University, Stanford, CA, December 2005.
Available as: PDF
Exposing Speculative Thread Parallelism in SPEC2000
Manohar Prabhu and Kunle Olukotun
Proceedings of the 2005 Principles and Practices of Parallel Programming, Chicago, IL, June 2005.
Available as: PDF
The Jrpm System for Dynamically Parallelizing Java Programs
Mike Chen and Kunle Olukotun
Special Issue of IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, Nov./Dec. 2003.
Available as: PDF
Using Thread-Level Speculation to Simplify Manual Parallelization
Manohar Prabhu and Kunle Olukotun
Proceedings of the 2003 Principles and Practices of Parallel Programming, San Diego, CA, June 2003.
Available as: PDF
The Jrpm System for Dynamically Parallelizing Java Programs
Mike Chen and Kunle Olukotun
Proceedings of the 30th International Symposium on Computer Architecture, San Diego, CA, June 2003.
Available as: PDF
TEST: A Tracer for Extracting Speculative Threads
Mike Chen and Kunle Olukotun
The 2003 International Symposium on Code Generation and Optimization, San Francisco, CA, March 2003.
Available as: PDF
The Stanford Hydra CMP
by Lance Hammond, Ben Hubbert , Michael Siu, Manohar Prabhu , Mike Chen , and Kunle Olukotun
IEEE MICRO Magazine, March-April 2000, and presented at Hot Chips 11, August 1999.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Talk slides available as: PDF Compressed PDF Postscript Compressed Postscript
Improving the Performance of Speculatively Parallel Applications on the Hydra CMP
by Kunle Olukotun, Lance Hammond, and Mark Willey
Proceedings of the 1999 ACM International Conference on Supercomputing, Rhodes, Greece, June 1999.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Exploiting Method-Level Parallelism in Single-Threaded Java Programs
by Mike Chen and Kunle Olukotun
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 1998.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Data Speculation Support for a Chip Multiprocessor
by Lance Hammond, Mark Willey, and Kunle Olukotun
Proceedings of the Eighth ACM Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, October 1998.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Talk slides available as: PDF Compressed PDF Postscript Compressed Postscript
Considerations in the Design of Hydra: A Multiprocessor-on-a-Chip Microarchitecture
by Lance Hammond, and Kunle Olukotun
Stanford University Computer Systems Lab Technical Report CSL-TR-98-749, February 1998.
Available as: PDF Compressed PDF Postscript Compressed Postscript
A Single-Chip Multiprocessor
Lance Hammond, Basem A. Nayfeh and Kunle Olukotun
IEEE Computer Special Issue on "Billion-Transistor Processors", September 1997.
Available as: PDF Compressed PDF Postscript Compressed Postscript
A Single Chip Multiprocessor Integrated with DRAM
Tadaaki Yamauchi, Lance Hammond and Kunle Olukotun
Workshop on Mixing Logic and DRAM preceding the 24th International Symposium on Computer Architecture, June 1997.
Available as: PDF Compressed PDF Postscript Compressed Postscript
or as published in Stanford University Computer Systems Lab Technical Report CSL-TR-97-731, August 1997.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor
Jeffery Oplinger, David Heine, Shih-Wei Liao, Basem A. Nayfeh , Monica Lam and Kunle Olukotun
Stanford University Computer Systems Lab Technical Report CSL-TR-97-715, February 1997.
Available as: PDF Compressed PDF Postscript Compressed Postscript
The Case for a Single-Chip Multiprocessor
Kunle Olukotun, Basem A. Nayfeh , Lance Hammond, Ken Wilson and Kun-Yung Chang
Proceedings of the Seventh International Symposium on Architectural Support for Parallel Languages and Operating Systems, October 1996.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Evaluation of Design Alternatives for a Multiprocessor Microprocessor
Basem A. Nayfeh , Lance Hammond and Kunle Olukotun
Proceedings of the 23rd International Symposium on Computer Architecture, May 1996.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Rationale and Design of the Hydra Multiprocessor
Note: This is the original MCM based design
Kunle Olukotun, Jules Bergmann, Kun-Yung Chang and Basem A. Nayfeh
Stanford University Computer Systems Lab Technical Report CSL-TR-94-645, 1994.
Available as: Postscript Compressed Postscript

General Computer Architecture Publications from our group:

Niagara: A 32-Way Multithreaded SPARC Processor
Poonacha Kongetira, Kathirgamar Aingaran, and Kunle Olukotun
IEEE MICRO Magazine, March-April 2005, and presented at Hot Chips 16, August 2004.
Available as: PDF
A Flexible, Efficient Concurrent Garbage Collector for Speculative Thread Processors
Mike Chen and Kunle Olukotun
Stanford University Computer Systems Lab Technical Report CSL-TR-03-K01, December 2003.
Available as: PDF
Targeting Dynamic Compilation for Embedded Systems
Mike Chen and Kunle Olukotun
2nd Java Virtual Machine Research and Technology Symposium, San Francisco, CA, August 2002.
Available as: PDF
Exploiting Coarse-Grain Parallelism in the MPEG-2 Algorithm
Eiji Iwata and Kunle Olukotun
Stanford University Computer Systems Lab Technical Report CSL-TR-98-771, September 1998.
Available as: PDF Compressed PDF Postscript Compressed Postscript
A Quantitative Analysis of Recongurable Coprocessors for Multimedia Applications
Takashi Miyamori and Kunle Olukotun
Proceedings of the 6th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, April 1998.
Available as: PDF Compressed PDF Postscript Compressed Postscript
REMARC: Recongurable Multimedia Array Coprocessor
Takashi Miyamori and Kunle Olukotun
Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 1998.
Available as: PDF Compressed PDF Postscript Compressed Postscript
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
by Tadaaki Yamauchi, Lance Hammond, and Kunle Olukotun
Proceedings of the 19th Conference on Advanced Research in VLSI, September 1997.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Designing High-Bandwidth On-Chip Caches
Kenneth M. Wilson and Kunle Olukotun
Proceedings of the 24th International Symposium on Computer Architecture, June 1997.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors
Kenneth M. Wilson, Kunle Olukotun and Mendel Rosenblum
Proceedings of the 23rd International Symposium on Computer Architecture, May 1996.
Available as: PDF Compressed PDF Postscript Compressed Postscript
The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors
Basem A. Nayfeh , Kunle Olukotun and Jaswinder Pal Singh
Proceedings of the Second Annual Symposium on High Performance Computer Architecture, February 1996.
Available as:
The Benefits of Clustering in Shared Address Space Multiprocessors: An Applications Driven Investigation
Andrew J. Erlichson, Basem A. Nayfeh , Jaswinder Pal Singh and Kunle Olukotun
Proceedings of Supercomputing'95, December 1995.
Available as: PDF Compressed PDF Postscript Compressed Postscript
Exploring the Design Space for a Shared-Cache Multiprocessor
Basem A. Nayfeh and Kunle Olukotun
Proceedings of the 21st International Symposium on Computer Architecture, February 1994.
Available as: PDF Compressed PDF Postscript Compressed Postscript